The present invention relates to a method of manufacturing a semiconductor device, which includes the step of connecting source and drain regions of an MIS semiconductor device to polysilicon wiring layers.
Multilayer wiring techniques have been recently employed to increase the packing density of semiconductor devices. Together with this, a new and improved MOS semiconductor device has been developed. This device has polysilicon wiring layers connected to its source and drain regions. A conventional MOS semiconductor device (e.g., an n-channel MOS semiconductor device) is manufactured as follows.
After a field oxide film as an element isolation region is formed in a major surface of a N-type silicon substrate to surround an island region, thermal oxidation is performed to form a gate oxide film on the island region. Subsequently, a polysilicon film as a gate electrode material is formed to cover the entire surface of the substrate and patterned to form a gate electrode. An n-type impurity, e.g., phosphorus is ion-implanted in part of the island region by using the field oxide film and the gate electrode as masks. The ion-implanted regions are activated to form N.sup.+ -type source and drain regions. A CVD-SiO.sub.2 film as an insulating layer is formed on the major surface of the substrate, and contact holes are formed in the CVD-SiO.sub.2 film at positions corresponding to the source and drain regions. A poly-crystalline silicon (polysilicon) film is formed to cover the entire surface of the resultant structure. Phosphorus diffusion or ion implantation is performed in the polysilicon film, and annealing is then performed at a temperature of 950.degree. C. or higher to thermally break down a natural oxide film formed at an interface between the N.sup.+ -type source and drain regions and the polysilicon film, thereby establishing an ohmic contact therebetween. Thereafter, the polysilicon film is patterned to form source and drain electrodes electrically connected to the source and drain regions, respectively.
In the conventional MOS semiconductor device, the source and drain regions must be shallow to increase the packing density. For this purpose, low temperature annealing is performed to form the source and drain regions, thereby preventing the impurity from redistribution. For this reason, unlike in the conventional technique, high temperature annealing cannot be performed. As a result, the natural oxide film formed at the interface between the source and drain regions and the polysilicon film cannot be sufficiently broken down. Therefore, no ohmic contact can be established between the source and drain regions and the polysilicon wiring layer.